Electronic memories usually operate with two logic levels 1 and 0. For dynamic random access memory (DRAM memory), these levels correspond to the charged or uncharged state of a capacitor. Reading the memory cell destroys the state of this memory cell since the charges stored in the capacitor are used as a read signal. In addition, for the sake of the memory cell density, the capacitance of the capacitor is low, and it is then impossible to differentiate several charge levels of the capacitor. Moreover, because of the various leakage currents associated with the control devices, the charge on the capacitor decreases and is not stable with time.
A memory cell of the DRAM type must be as small as possible for the sake of density. It consists of an access transistor controlling the charging or the discharging of a capacitor. This capacitor must, on the one hand, have a maximum capacitance and, on the other hand, occupy a minimum surface. Currently, the capacitor is made either in the silicon substrate or in the upper interconnect layers of the integrated circuit.
In the first case, the capacitor is located at the side of the access transistor. In the second case, the capacitor occupies a large volume above the transistor, a volume which cannot be used to make interconnections in the integrated circuit.
In both cases, the density of the memory cell, that is to say its overall size, is affected thereby.